FPGA中关于RAM的伪双端端口的小实验

timescale 1ns / 1ps //顶层 module double_ram( input sysclk, input rst_n , output [7:0] doutb ); wire wea; wire enb; wire [5:0] addrb; wire [5:0] addra; wire[7:0] dina; ram_r ram_r_u( . sysclk ( sysclk) , . rst_n ( rst_n ) , . enb ( enb ) , . addrb ( addrb ) ); ram_w ram_w_u( . sysclk ( sysclk) , . rst_n ( rst_n ) , . wea ( wea ) , . enb ( enb ) , . dina ( dina ) , . addra ( addra ) ); duble_ram your_instance_name ( .clka(sysclk), // input wire clka .wea(wea), // input wire [0 : 0] wea .addra(addra), // input wire [5 : 0] addra .dina(dina), // input wire [7 : 0] dina .clkb(sysclk), // input wire clkb .enb(enb), // input wire enb .addrb(addrb), // input wire [5 : 0] addrb .doutb(doutb) // output wire [7 : 0] doutb ); endmodule写模块timescale 1ns / 1ps module ram_w( input sysclk , input rst_n , input [0 : 0] wea , output enb , output [7 : 0] dina , output reg [5:0] addra ); //wea assign wea1; //enb assign enb (addra32)?1:0; //addra always(posedge sysclk) if(!rst_n) addra0; else if(addra63) addra0; else addraaddra1; //dina assign dina {2b00, addra}; endmodule读模块timescale 1ns / 1ps module ram_r( input sysclk, input rst_n, input enb, output reg [5:0] addrb ); //addrb always(posedge sysclk) if(!rst_n) addrb0; else if(enb)begin if(addrb63) addrb0; else addrbaddrb1; end else addrbaddrb; endmodule