![verilog HDLBits刷题[Karnaugh Map to Circuit]“Exams/2012 q1g”---Kamaugh map](images/news1.jpg)
题目module top_module ( input [4:1] x, output f ); assign f(~x[2](~x[4]))|(~x[1]x[3])|(x[2]x[3]x[4]); endmodule
verilog HDLBits刷题[Karnaugh Map to Circuit]“Exams/2012 q1g”---Kamaugh map
题目module top_module ( input [4:1] x, output f ); assign f(~x[2](~x[4]))|(~x[1]x[3])|(x[2]x[3]x[4]); endmodule
