参考资料ICC2 User Guide Version M-2016.12-SP4• Defining the Search Pathset_app_var search_path {./ ../syn/netlist \ ../../SK_PDK/HB180_7T_RVT_1P8V_v1.0.1.0/LIBERTY_DB} set_app_var link_library {* HB180_7T_RVT_1P8V_FF_1P98V_M40C.db \ HB180_7T_RVT_1P8V_SS_1P62V_125C.db \ HB180_7T_RVT_1P8V_TT_1P80V_25C.db}• Working With Design Libraries可以把这个理解成创建一个工程目录后面做的每一步block都会存储在这个目录中当open block时指定这个lib就可以看到存储的各个block, 这个Design Libraries包括Technology file和Reference libraries.其中Technology file,可以从PDK中找到Reference libraries需要用icc2_lm_shell通过其他文件来转换。create_lib -technology /data/workspace/lcc/project/SK_PDK/HB180_7T_RVT_1P8V_v1.0.1.0/TECHFILE_ICC/HB180_7T_UTHICK_M4.tf \ -ref_libs ./my.ndm/ pr可能用到其他的命令如下open_lib pr 可以同时打开多个libsave_lib prclose_lib prcurrent_lib pr(当打开多个lib时指定当前工作的lib)• Working With Designs读取verilog的同时会自动创建一个blockread_verilog -top digital_top ../syn/netlist/digital_top.v可能用到其他的命令如下create_block, open_block, current_block, save_block, close_block• Annotating the Floorplan Informationread_def floorplan.def• Annotating the Scan Chain Information如果设计中不用scan chain则用第二条命令来关闭不然place_opt时会报错read_def ./scan.def #if the design do not include scan chain this command need to be set set_app_options -name place.coarse.continue_on_missing_scandef -value true• Preparing for Timing Analysisremove_scenarios -all read_parasitic_tech -tlup /data/workspace/lcc/project/SK_PDK/HB180ELL_PDK_IC6.1_v1.11.3.1/LPE/StartRCXT/TM_35K/top_metal4/HB180ELL_RCXT_v1.5.0_TM_35K_M4_SLOW.tluplus \ -layermap /data/workspace/lcc/project/SK_PDK/HB180_7T_RVT_1P8V_v1.0.1.0/TECHFILE_ICC/TECH2ITF_MAP \ -name slow create_mode fast_mode create_corner fast_corner set_parasitic_parameters -corners fast_corner -early_spec fast -late_spec slow create_scenario -mode fast_mode -corner fast_corner -name fast_scenario current_scenario fast_scenario set_scenario_status -setup true -hold true -leakage_power true -dynamic_power true -active true fast_scenario read_sdc ../syn/netlist/digital_top.sdc place_opt• Specifying the Power Intent这章节主要讲的是UPF多电源域的设计后面再学习暂时跳过。• Preparing the Power Network这章节主要讲的是电源后面再学习暂时跳过。• Preparing for Optimization对设计进行的一些限定设置包括以下• Restricting Library Cell Usageset_lib_cell_purpose -include none lib_cells report_target_library_subset• Preventing Optimization on Cells and Netsset_dont_touch [get_cells cell_name] true set_dont_touch [get_nets net_name] true report_dont_touch -all• Restricting Optimization on Cellsset_size_only [get_cells cell_name] true report_size_only -all• Preserving Pin Names During Sizing• Isolating Input and Output Ports• Preparing for Percentage Low-Threshold-Voltage Optimization配置多种阈值器件的占比不常用暂时先不管。• Annotating the Switching Activity通过读取read_saif文件来进行功耗的优化不常用暂时先不管。• Specifying the Routing Resources定义布线层数规则等等暂时先不管。• Enabling Multicore Processing对服务器进行相关的配置暂时先不管。
ICC2学习笔记之Preparing the Design
参考资料ICC2 User Guide Version M-2016.12-SP4• Defining the Search Pathset_app_var search_path {./ ../syn/netlist \ ../../SK_PDK/HB180_7T_RVT_1P8V_v1.0.1.0/LIBERTY_DB} set_app_var link_library {* HB180_7T_RVT_1P8V_FF_1P98V_M40C.db \ HB180_7T_RVT_1P8V_SS_1P62V_125C.db \ HB180_7T_RVT_1P8V_TT_1P80V_25C.db}• Working With Design Libraries可以把这个理解成创建一个工程目录后面做的每一步block都会存储在这个目录中当open block时指定这个lib就可以看到存储的各个block, 这个Design Libraries包括Technology file和Reference libraries.其中Technology file,可以从PDK中找到Reference libraries需要用icc2_lm_shell通过其他文件来转换。create_lib -technology /data/workspace/lcc/project/SK_PDK/HB180_7T_RVT_1P8V_v1.0.1.0/TECHFILE_ICC/HB180_7T_UTHICK_M4.tf \ -ref_libs ./my.ndm/ pr可能用到其他的命令如下open_lib pr 可以同时打开多个libsave_lib prclose_lib prcurrent_lib pr(当打开多个lib时指定当前工作的lib)• Working With Designs读取verilog的同时会自动创建一个blockread_verilog -top digital_top ../syn/netlist/digital_top.v可能用到其他的命令如下create_block, open_block, current_block, save_block, close_block• Annotating the Floorplan Informationread_def floorplan.def• Annotating the Scan Chain Information如果设计中不用scan chain则用第二条命令来关闭不然place_opt时会报错read_def ./scan.def #if the design do not include scan chain this command need to be set set_app_options -name place.coarse.continue_on_missing_scandef -value true• Preparing for Timing Analysisremove_scenarios -all read_parasitic_tech -tlup /data/workspace/lcc/project/SK_PDK/HB180ELL_PDK_IC6.1_v1.11.3.1/LPE/StartRCXT/TM_35K/top_metal4/HB180ELL_RCXT_v1.5.0_TM_35K_M4_SLOW.tluplus \ -layermap /data/workspace/lcc/project/SK_PDK/HB180_7T_RVT_1P8V_v1.0.1.0/TECHFILE_ICC/TECH2ITF_MAP \ -name slow create_mode fast_mode create_corner fast_corner set_parasitic_parameters -corners fast_corner -early_spec fast -late_spec slow create_scenario -mode fast_mode -corner fast_corner -name fast_scenario current_scenario fast_scenario set_scenario_status -setup true -hold true -leakage_power true -dynamic_power true -active true fast_scenario read_sdc ../syn/netlist/digital_top.sdc place_opt• Specifying the Power Intent这章节主要讲的是UPF多电源域的设计后面再学习暂时跳过。• Preparing the Power Network这章节主要讲的是电源后面再学习暂时跳过。• Preparing for Optimization对设计进行的一些限定设置包括以下• Restricting Library Cell Usageset_lib_cell_purpose -include none lib_cells report_target_library_subset• Preventing Optimization on Cells and Netsset_dont_touch [get_cells cell_name] true set_dont_touch [get_nets net_name] true report_dont_touch -all• Restricting Optimization on Cellsset_size_only [get_cells cell_name] true report_size_only -all• Preserving Pin Names During Sizing• Isolating Input and Output Ports• Preparing for Percentage Low-Threshold-Voltage Optimization配置多种阈值器件的占比不常用暂时先不管。• Annotating the Switching Activity通过读取read_saif文件来进行功耗的优化不常用暂时先不管。• Specifying the Routing Resources定义布线层数规则等等暂时先不管。• Enabling Multicore Processing对服务器进行相关的配置暂时先不管。
