verilog HDLBits刷题[Finite State Machines]“Fsm3comb”---Simple state transitions

1、题目The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A2b00, B2b01, C2b10, D2b11.Implement only the state transition logic and output logic(the combinational logic portion) for this state machine. Given the current state (state), compute thenext_stateand output (out) based on the state transition table.StateNext stateOutputin0in1AAB0BCB0CAD0DCB12、代码module top_module( input in, input [1:0] state, output [1:0] next_state, output out); // parameter A2b00, B2b01, C2b10, D2b11; always(*)begin case(state) A: next_statein?B:A; B:next_statein?B:C; C:next_statein?D:A; D:next_statein?B:C; endcase end assign out(stateD); endmodule