![verilog HDLBits刷题[Finite State Machines]“Fsm serialdp”---Serial receiver with parity checking](images/news1.jpg)
1、题目See also: Serial receiver and datapathWe want to add parity checking to the serial receiver. Parity checking adds one extra bit after each data byte. We will use odd parity, where the number of 1s in the 9 bits received must be odd. For example, 101001011 satisfies odd parity (there are 5 1s), but 001001011 does not.Change your FSM and datapath to perform odd parity checking. Assert the done signal only if a byte is correctly receivedandits parity check passes. Like the serial receiver FSM, this FSM needs to identify the start bit, wait for all 9 (data and parity) bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.You are provided with the following module that can be used to calculate the parity of the input stream (Its a TFF with reset). The intended use is that it should be given the input bit stream, and reset at appropriate times so it counts the number of 1 bits in each byte.module parity ( input clk, input reset, input in, output reg odd); always (posedge clk) if (reset) odd 0; else if (in) odd ~odd; endmoduleNote that the serial protocol sends the least significant bit first, and the parity bit after the 8 data bits.2、分析分析失败还是不太理解代码根据网上的进行了部分修改先留着什么时候理解了再来看看3、代码module top_module( input clk, input in, input reset, // Synchronous reset output [7:0] out_byte, output reg done ); // parameter IDEL5d0; parameter DATA15d2,DATA25d3,DATA35d4,DATA45d5,DATA55d6,DATA65d7,DATA75d8,DATA85d9; parameter PAR5d10,DECTION5d11,WAIT_STOP5d12,STOP5d13; reg [4:0]state,next_state; reg [7:0]out_byte_r; reg odd; reg parity_reset; always(posedge clk) if(reset) stateIDEL; else statenext_state; always(*)begin case(state) IDEL:next_statein?IDEL:DATA1; DATA1:next_stateDATA2; DATA2:next_stateDATA3; DATA3:next_stateDATA4; DATA4:next_stateDATA5; DATA5:next_stateDATA6; DATA6:next_stateDATA7; DATA7:next_stateDATA8; DATA8:next_statePAR; PAR:next_stateDECTION; DECTION:next_statein?STOP:WAIT_STOP; WAIT_STOP:next_statein?IDEL:WAIT_STOP; STOP:next_statein?IDEL:DATA1; default:next_stateIDEL; endcase end always(posedge clk)begin case(next_state)//不是state default:out_byte_rout_byte_r; endcase end always(posedge clk)begin if(reset)begin done0; parity_reset1; out_byte_r8d0; end else begin case(state) IDEL:parity_resetin?1:0;//空闲状态奇偶校验复位有效 DATA1:out_byte_r[0]in;//数据状态奇偶校验复位无效存入数据 DATA2:out_byte_r[1]in; DATA3:out_byte_r[2]in; DATA4:out_byte_r[3]in; DATA5:out_byte_r[4]in; DATA6:out_byte_r[5]in; DATA7:out_byte_r[6]in; DATA8:out_byte_r[7]in; PAR:parity_reset1;//奇偶校验状态奇偶校验复位有效 DECTION:donein?odd:0; STOP:begin done0;parity_resetin?1:0;;end WAIT_STOP:begin done0;parity_reset1;end default:begin done0; parity_reset1; out_byte_rout_byte_r; end endcase end end assign out_bytedone?out_byte_r:8d0; parity inst(clk,parity_reset,in,odd); endmodule
verilog HDLBits刷题[Finite State Machines]“Fsm serialdp”---Serial receiver with parity checking
1、题目See also: Serial receiver and datapathWe want to add parity checking to the serial receiver. Parity checking adds one extra bit after each data byte. We will use odd parity, where the number of 1s in the 9 bits received must be odd. For example, 101001011 satisfies odd parity (there are 5 1s), but 001001011 does not.Change your FSM and datapath to perform odd parity checking. Assert the done signal only if a byte is correctly receivedandits parity check passes. Like the serial receiver FSM, this FSM needs to identify the start bit, wait for all 9 (data and parity) bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.You are provided with the following module that can be used to calculate the parity of the input stream (Its a TFF with reset). The intended use is that it should be given the input bit stream, and reset at appropriate times so it counts the number of 1 bits in each byte.module parity ( input clk, input reset, input in, output reg odd); always (posedge clk) if (reset) odd 0; else if (in) odd ~odd; endmoduleNote that the serial protocol sends the least significant bit first, and the parity bit after the 8 data bits.2、分析分析失败还是不太理解代码根据网上的进行了部分修改先留着什么时候理解了再来看看3、代码module top_module( input clk, input in, input reset, // Synchronous reset output [7:0] out_byte, output reg done ); // parameter IDEL5d0; parameter DATA15d2,DATA25d3,DATA35d4,DATA45d5,DATA55d6,DATA65d7,DATA75d8,DATA85d9; parameter PAR5d10,DECTION5d11,WAIT_STOP5d12,STOP5d13; reg [4:0]state,next_state; reg [7:0]out_byte_r; reg odd; reg parity_reset; always(posedge clk) if(reset) stateIDEL; else statenext_state; always(*)begin case(state) IDEL:next_statein?IDEL:DATA1; DATA1:next_stateDATA2; DATA2:next_stateDATA3; DATA3:next_stateDATA4; DATA4:next_stateDATA5; DATA5:next_stateDATA6; DATA6:next_stateDATA7; DATA7:next_stateDATA8; DATA8:next_statePAR; PAR:next_stateDECTION; DECTION:next_statein?STOP:WAIT_STOP; WAIT_STOP:next_statein?IDEL:WAIT_STOP; STOP:next_statein?IDEL:DATA1; default:next_stateIDEL; endcase end always(posedge clk)begin case(next_state)//不是state default:out_byte_rout_byte_r; endcase end always(posedge clk)begin if(reset)begin done0; parity_reset1; out_byte_r8d0; end else begin case(state) IDEL:parity_resetin?1:0;//空闲状态奇偶校验复位有效 DATA1:out_byte_r[0]in;//数据状态奇偶校验复位无效存入数据 DATA2:out_byte_r[1]in; DATA3:out_byte_r[2]in; DATA4:out_byte_r[3]in; DATA5:out_byte_r[4]in; DATA6:out_byte_r[5]in; DATA7:out_byte_r[6]in; DATA8:out_byte_r[7]in; PAR:parity_reset1;//奇偶校验状态奇偶校验复位有效 DECTION:donein?odd:0; STOP:begin done0;parity_resetin?1:0;;end WAIT_STOP:begin done0;parity_reset1;end default:begin done0; parity_reset1; out_byte_rout_byte_r; end endcase end end assign out_bytedone?out_byte_r:8d0; parity inst(clk,parity_reset,in,odd); endmodule
